----------------------------------------------------------------------------------
-- Company:				EIFR
-- Engineer: 			Simon Nissille
-- 
-- Create Date:    	22:44:13 04/26/2009 
-- Module Name:    	displayTime - Behavioral 
-- Project Name: 	 	iTimer
-- Target Devices: 	Spartan 2 50
-- Tool versions:  	1.0
-- Description: 	 	Module um die Zeit die man auf einem 13 bits bus bekommt
--							"busTimer" auf 4 Displays anzuzeigen.
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity displayTime is
    Port ( busTimer : in  STD_LOGIC_VECTOR (12 downto 0);
			  clockInput : in STD_LOGIC;
			  busMode : in STD_LOGIC_VECTOR(1 downto 0);
           segment1 : out  STD_LOGIC_VECTOR (3 downto 0):="1111";
           segment2 : out  STD_LOGIC_VECTOR (3 downto 0):="1111";
           segment3 : out  STD_LOGIC_VECTOR (3 downto 0):="1111";
           segment4 : out  STD_LOGIC_VECTOR (3 downto 0):="1111" );
end displayTime;

architecture Behavioral of displayTime is

SIGNAL tempSegment1,tempSegment2,tempSegment3,tempSegment4:STD_LOGIC_VECTOR(3 downto 0):="0000";
SIGNAL oldTime,timeModified:STD_LOGIC_VECTOR (12 downto 0);
SIGNAL reStartTime: STD_LOGIC:='1';
SIGNAL busWaitedTime : STD_LOGIC_VECTOR (11 downto 0);
TYPE zstEdit IS (updateDisplay,waitInDisplay,waitInShutDown);
SIGNAL actualZst:zstEdit:= updateDisplay; 

begin

waitedTimeComponent:ENTITY WORK.waitedTime PORT Map (clockInput => clockInput, reStartTime =>  reStartTime, busWaitedTime => busWaitedTime);




timeTransform:PROCESS(clockInput)
	BEGIN
		IF rising_edge(clockInput) THEN 
			IF busTimer /= oldTime  THEN
				oldTime <= busTimer;
				timeModified <= busTimer;
				tempSegment1 <= "0000";
				tempSegment2 <= "0000";
				tempSegment3 <= "0000";
				tempSegment4 <= "0000";
			ELSE
				IF timeModified > conv_std_logic_vector(599, 14) THEN
					tempSegment1 <= tempSegment1 + 1 ;
					timeModified <= timeModified - conv_std_logic_vector(600, 13);
				ELSIF timeModified > conv_std_logic_vector(59, 14) THEN
					tempSegment2 <= tempSegment2 + 1 ;
					timeModified <= timeModified - conv_std_logic_vector(60, 13);
				ElSIF timeModified > conv_std_logic_vector(9, 14)THEN
					tempSegment3 <= tempSegment3 + 1 ;
					timeModified <= timeModified - conv_std_logic_vector(10, 13);
				ELSE
					IF busMode = "00" THEN
						IF actualZst = updateDisplay THEN 
							segment1 <= tempSegment1;			
							segment2 <= tempSegment2;
							segment3 <= tempSegment3;
							segment4 <= timeModified(3 downto 0 ) ;
							reStartTime<= '0';
							actualZst<= waitInDisplay;
						ELSIF actualZst = waitInDisplay THEN
							segment1 <= tempSegment1;			
							segment2 <= tempSegment2;
							segment3 <= tempSegment3;
							segment4 <= timeModified(3 downto 0 ) ;
							IF conv_integer(busWaitedTime) >= 800 THEN
								actualZst <= waitInShutDown;
							END IF;
						ELSIF actualZst = waitInShutDown THEN
							segment1 <= "1111";
							segment2 <= "1111";
							segment3 <= "1111";
							segment4 <= "1111";
							IF conv_integer(busWaitedTime) >= 850 THEN
								reStartTime<= '1';
								actualZst <= updateDisplay;
							END IF;
						END IF;
					ELSE
						segment1 <= tempSegment1;
						segment2 <= tempSegment2;
						segment3 <= tempSegment3;
						segment4 <= timeModified(3 downto 0 );
					END IF;
				END IF;			
			END IF;
		
		END IF;
	END PROCESS timeTransform;
end Behavioral;
